{"title":"低成本手持逻辑分析仪的设计与实现","authors":"Sujur Alagar Ramalingam","doi":"10.1109/IEEEGCC.2013.6705738","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of a Handheld Logic Analyzer. It is based on the FPGA to capture 9 channel digital data and the ARM7 processor as a master controller, which reads these 9 channel data from the FPGA and sends them to the color graphics LCD to display as 9 channel waveforms. The system features include the ability to capture the data up to 10 MHz and the user can select the data sample rate and also measure the time/period of any of the 9 waveforms. This is a simple, standalone, handheld and cost effective Logic timing Analyzer specifically designed for students, which is easy to use and aids their learning process.","PeriodicalId":316751,"journal":{"name":"2013 7th IEEE GCC Conference and Exhibition (GCC)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design and implementation of low cost Hand-held Logic Analyzer\",\"authors\":\"Sujur Alagar Ramalingam\",\"doi\":\"10.1109/IEEEGCC.2013.6705738\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of a Handheld Logic Analyzer. It is based on the FPGA to capture 9 channel digital data and the ARM7 processor as a master controller, which reads these 9 channel data from the FPGA and sends them to the color graphics LCD to display as 9 channel waveforms. The system features include the ability to capture the data up to 10 MHz and the user can select the data sample rate and also measure the time/period of any of the 9 waveforms. This is a simple, standalone, handheld and cost effective Logic timing Analyzer specifically designed for students, which is easy to use and aids their learning process.\",\"PeriodicalId\":316751,\"journal\":{\"name\":\"2013 7th IEEE GCC Conference and Exhibition (GCC)\",\"volume\":\"211 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 7th IEEE GCC Conference and Exhibition (GCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEEEGCC.2013.6705738\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 7th IEEE GCC Conference and Exhibition (GCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEEGCC.2013.6705738","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of low cost Hand-held Logic Analyzer
This paper presents the design and implementation of a Handheld Logic Analyzer. It is based on the FPGA to capture 9 channel digital data and the ARM7 processor as a master controller, which reads these 9 channel data from the FPGA and sends them to the color graphics LCD to display as 9 channel waveforms. The system features include the ability to capture the data up to 10 MHz and the user can select the data sample rate and also measure the time/period of any of the 9 waveforms. This is a simple, standalone, handheld and cost effective Logic timing Analyzer specifically designed for students, which is easy to use and aids their learning process.