从Java到FPGA:使用Intel HARP系统的经验

Pedro Caldeira, J. Penha, L. Bragança, Ricardo Ferreira, J. Nacif, R. Ferreira, Fernando Magno Quintão Pereira
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引用次数: 10

摘要

近年来,现场可编程门阵列(fpga)的普及程度激增。程序员可以使用它们来开发不仅在时间上高效,而且在能源上高效的高性能系统。然而,fpga编程仍然是一项艰巨的任务。尽管现在有OpenCL接口来合成这些硬件,但高级编程语言,如Java、c#或Python仍然离它们很远。在本文中,我们描述了一个编译器,以及它支持的运行时环境,它减少了这个距离,将用Java编写的功能代码转换为Intel HARP平台。因此,我们带来了两个贡献。首先,函数式库是弥合高级编程习惯和fpga之间差距的良好起点。其次,这个系统本身的实现,包括编译器,它的中间表示,以及所有必要的运行时支持,以保护开发人员免受在主机CPU和加速器之间来回传输数据的任务。为了证明我们的系统的有效性,我们使用它来实现不同的基准测试,用于图像处理和数据挖掘。对于大的输入,我们可以观察到在所有基准测试中Java虚拟机的速度提高了20倍。根据我们编译的目标函数,这个加速可以达到280x。
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From Java to FPGA: An Experience with the Intel HARP System
Recent years have seen a surge in the popularity of Field-Programmable Gate Arrays (FPGAs). Programmers can use them to develop high-performance systems that are not only efficient in time, but also in energy. Yet, programming FPGAs remains a difficult task. Even though there exist today OpenCL interfaces to synthesize such hardware, higher-level programming languages, such as Java, C# or Python remain distant from them. In this paper, we describe a compiler, and its supporting runtime environment, that reduces this distance, translating functional code written in Java to the Intel HARP platform. Thus, we bring two contributions. First, the insight that a functional-style library is a good starting point to bridge the gap between high-level programming idioms and FPGAs. Second, the implementation of this system itself, including the compiler, its intermediate representation, and all the runtime support necessary to shield developers from the task of transferring data back and forth between the host CPU and the accelerator. To demonstrate the effectiveness of our system, we have used it to implement different benchmarks, used in image processing and data-mining. For large inputs, we can observe consistent 20x speedups over the Java Virtual Machine across all our benchmarks. Depending on the target function that we compile, this speedup can achieve 280x.
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Assessing Time Predictability Features of ARM Big. LITTLE Multicores Impacts of Three Soft-Fault Models on Hybrid Parallel Asynchronous Iterative Methods Predicting the Performance Impact of Increasing Memory Bandwidth for Scientific Workflows From Java to FPGA: An Experience with the Intel HARP System Copyright
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