{"title":"直接数字频率合成器用于介质电泳","authors":"F. Heredia, C. Carbajal, S. Martinez","doi":"10.1109/CERMA.2008.58","DOIUrl":null,"url":null,"abstract":"It is common practice to use sinusoidal signals for generating the electric fields needed for particle manipulation using dielectrophoresis (DEP). A direct digital frequency synthesizer (DFFS) is well suited for this application because of its fast switching speed, high resolution, small size and low power. The focus of this paper is on design, analysis, simulation and implementation of a DDFS, using Altera tools. The proposed architecture uses a unipolar digital-to-analog converter (DAC). Memory size is reduced more than 75 percent using quadrant compression. To decrease the amount of hardware even further, the phase generated by the phase accumulator is truncated before it is used by the ROM. Dither is added in order to get higher spurious free dynamic range. Further reduction is achieved storing in the ROM only the difference between the sinusoidal function and the phase.","PeriodicalId":126172,"journal":{"name":"2008 Electronics, Robotics and Automotive Mechanics Conference (CERMA '08)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Direct Digital-Frequency Synthesizer for Dielectrophoresis\",\"authors\":\"F. Heredia, C. Carbajal, S. Martinez\",\"doi\":\"10.1109/CERMA.2008.58\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is common practice to use sinusoidal signals for generating the electric fields needed for particle manipulation using dielectrophoresis (DEP). A direct digital frequency synthesizer (DFFS) is well suited for this application because of its fast switching speed, high resolution, small size and low power. The focus of this paper is on design, analysis, simulation and implementation of a DDFS, using Altera tools. The proposed architecture uses a unipolar digital-to-analog converter (DAC). Memory size is reduced more than 75 percent using quadrant compression. To decrease the amount of hardware even further, the phase generated by the phase accumulator is truncated before it is used by the ROM. Dither is added in order to get higher spurious free dynamic range. Further reduction is achieved storing in the ROM only the difference between the sinusoidal function and the phase.\",\"PeriodicalId\":126172,\"journal\":{\"name\":\"2008 Electronics, Robotics and Automotive Mechanics Conference (CERMA '08)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-09-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 Electronics, Robotics and Automotive Mechanics Conference (CERMA '08)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CERMA.2008.58\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Electronics, Robotics and Automotive Mechanics Conference (CERMA '08)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CERMA.2008.58","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Direct Digital-Frequency Synthesizer for Dielectrophoresis
It is common practice to use sinusoidal signals for generating the electric fields needed for particle manipulation using dielectrophoresis (DEP). A direct digital frequency synthesizer (DFFS) is well suited for this application because of its fast switching speed, high resolution, small size and low power. The focus of this paper is on design, analysis, simulation and implementation of a DDFS, using Altera tools. The proposed architecture uses a unipolar digital-to-analog converter (DAC). Memory size is reduced more than 75 percent using quadrant compression. To decrease the amount of hardware even further, the phase generated by the phase accumulator is truncated before it is used by the ROM. Dither is added in order to get higher spurious free dynamic range. Further reduction is achieved storing in the ROM only the difference between the sinusoidal function and the phase.