Signal/Power Integrity Co-Simulation of DDR3 Memory Module

In this paper, a simulation methodology considering signal integrity (SI) and power integrity (PI) from the chip, package, and board levels of a double-data-rate three (DDR3) memory module is presented. For SI issues, the chip-package-board simulation indicates how to improve eye diagram by eliminating non-ideal effects of the most crucial part of the channel. For PI issues, the SI/PI co-simulation is concerned with the power distribution network (PDN) and the distribution of decoupling capacitors (De-Caps). In addition, the optimized set of de-caps by simulation provides a cost-effect way to meet the desired target impedance for acceptable simultaneous switching noise (SSN) generated in PDN due to I/O switching. Finally, the co-simulation methodology can indicate SI/PI problems before IC tape-out and reduce circuit design cycle as well.