Heeseok Lee, Hyungsoo Kim, Jingook Kim, Y. Jeong, Joungho Kim
{"title":"功率/地平面FDTD高效建模的等效电路表示与降维技术","authors":"Heeseok Lee, Hyungsoo Kim, Jingook Kim, Y. Jeong, Joungho Kim","doi":"10.1109/EPEP.2001.967632","DOIUrl":null,"url":null,"abstract":"We rigorously present a time-domain simulation method for the prediction of the simultaneous switching noise (SSN) in high-speed digital systems, using power/ground plane modeling of an arbitrarily shaped board or package.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Equivalent circuit representation and dimension reduction technique for efficient FDTD modeling of power/ground plane\",\"authors\":\"Heeseok Lee, Hyungsoo Kim, Jingook Kim, Y. Jeong, Joungho Kim\",\"doi\":\"10.1109/EPEP.2001.967632\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We rigorously present a time-domain simulation method for the prediction of the simultaneous switching noise (SSN) in high-speed digital systems, using power/ground plane modeling of an arbitrarily shaped board or package.\",\"PeriodicalId\":174339,\"journal\":{\"name\":\"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2001.967632\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2001.967632","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Equivalent circuit representation and dimension reduction technique for efficient FDTD modeling of power/ground plane
We rigorously present a time-domain simulation method for the prediction of the simultaneous switching noise (SSN) in high-speed digital systems, using power/ground plane modeling of an arbitrarily shaped board or package.