A new systolic array algorithm for memory-based VLSI array implementation of IDCT with high throughput rate and low complexity

A new systolic algorithm for memory-based parallel VLSI implementation of the inverse to discrete cosine transform (IDCT) is proposed. The new approach is based on a new formulation of an odd prime-length IDCT which uses two half-length cyclic convolutions with the same form which can be concurrently computed and were such reformulated that an efficient substitution of multipliers with small ROMs can be obtained. Using this algorithm, a new efficient VLSI implementation with outstanding performance in structural regularity, hardware cost of the PEs, average computation time, and I/O costs can be obtained. It has a much lower control complexity, and a simpler hardware structure.