Implementation of 9 bit Signed Vedic Multiplier on Zed Board

Multipliers are important components of most modern day processors. Vedic Algorithm to design processors has been implemented by several authors and present promising results. In the current work, we propose $\mathbf{3}\times \mathbf{3},\mathbf{5}\times \mathbf{5}$ and $\mathbf{9}\times\mathbf{9}$ multipliers based on Urdhva Tiryak $\mathbf{2}\times\mathbf{2},\mathbf{4}\times\mathbf{4}$ and $\pmb{8}\times \pmb{8}$ multipliers. The power consumption for signed and unsigned multipliers is found to be comparable.