Network-on-Chip: Challenges for the interconnect and I/O-architecture

3D ICs are emerging as a promising solution for scalability, power and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes a number of challenges with respect to cost, technological reliability, thermal budget, integration and so forth. Networks-on-chips (NoCs), which are thoroughly investigated in 2D SoCs design as scalable interconnects, are also well relevant to 3D IC Design. In this paper, special challenges for NoC interconnect architectures design, such as the need for high throughput and/or low latency, high reliability and low power consumption, are presented.