使记忆性神经网络加速器可靠

Ben Feinberg, Shibo Wang, Engin Ipek
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引用次数: 92

摘要

与其他监督学习模型相比,深度神经网络(dnn)由于在许多分类和回归任务上的优异性能,近年来引起了人们的极大兴趣。dnn通常需要大量的数据移动,从而导致性能和能量开销。解决这个问题的一个有希望的方法是设计一个基于原位模拟计算的加速器,利用忆阻电路的基本电学特性来执行矩阵向量乘法。近年来,模拟神经网络加速器在提高系统性能和能效方面显示出巨大的潜力。然而,检测和纠正内存模拟计算期间发生的错误在很大程度上仍未被探索。提供性能和能量改进的相同电气特性使这些系统特别容易受到错误的影响,这可能严重损害神经网络加速器的准确性。本文研究了一种新的基于算术码的模拟神经网络加速器纠错方案。该方案通过一个整数的乘法对数据进行编码,通过分配律保留了加法运算。错误检测和修正是通过模数运算和修正表查找来执行的。通过数据感知编码来利用错误的状态依赖性,以及通过了解计算的每个部分对整个系统精度的重要性,进一步改进了这个基本方案。通过观察到包含较少15的物理行不易受到错误的影响,所提出的方案以小于4.5%的面积和小于4.7%的能量开销增加了有效纠错能力。当应用于记忆性DNN加速器对MNIST和ILSVRC-2012数据集进行推理时,所提出的技术将各自的误分类率降低了1.5倍和1.1倍。
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Making Memristive Neural Network Accelerators Reliable
Deep neural networks (DNNs) have attracted substantial interest in recent years due to their superior performance on many classification and regression tasks as compared to other supervised learning models. DNNs often require a large amount of data movement, resulting in performance and energy overheads. One promising way to address this problem is to design an accelerator based on in-situ analog computing that leverages the fundamental electrical properties of memristive circuits to perform matrix-vector multiplication. Recent work on analog neural network accelerators has shown great potential in improving both the system performance and the energy efficiency. However, detecting and correcting the errors that occur during in-memory analog computation remains largely unexplored. The same electrical properties that provide the performance and energy improvements make these systems especially susceptible to errors, which can severely hurt the accuracy of the neural network accelerators. This paper examines a new error correction scheme for analog neural network accelerators based on arithmetic codes. The proposed scheme encodes the data through multiplication by an integer, which preserves addition operations through the distributive property. Error detection and correction are performed through a modulus operation and a correction table lookup. This basic scheme is further improved by data-aware encoding to exploit the state dependence of the errors, and by knowledge of how critical each portion of the computation is to overall system accuracy. By leveraging the observation that a physical row that contains fewer 1s is less susceptible to an error, the proposed scheme increases the effective error correction capability with less than 4.5% area and less than 4.7% energy overheads. When applied to a memristive DNN accelerator performing inference on the MNIST and ILSVRC-2012 datasets, the proposed technique reduces the respective misclassification rates by 1.5x and 1.1x.
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