Design and Performance Evaluation of Differential Ring Oscillators for Cognitive Radio receiver

In this work, three different configuration of Differential Ring Oscillator (DRO) are designed and compared in terms of tuning range, phase noise and power dissipation. SCL 180nm CMOS technology is utilized for design and analysis purpose under supply voltage constraint of 1.8 V. Three stage configuration of DRO exhibits a tuning range of 83.74 % (from 464 MHz to 2.85 GHz) and phase noise of -104.2 dBc/Hz (at 1 MHz offset) from 1 GHz carrier frequency. Among all 3 configurations, highest and lowest tuning percentage range are achieved by three stage and seven stage DRO, respectively. Seven stage DRO displays the best noise performance. The power consumption is lowest for three stage DRO and found to be 4.3 mW. Based on these results, it is evident that three stage DRO is suitable choice for low power, small area targeted frequency synthesizer design for Cognitive Radio receiver.