Wideband complementary CMOS VCO with capacitive-source-degeneration technique

This paper demonstrates a wideband complementary LC-VCO using capacitive-source-degeneration (CSD) technique for WiFi and LTE applications. A cross-coupling pair is required to generate suitable-gm but the parasitic capacitance of the pair leads to a reduction of capacitance ratio of varactors and thus, tuning range of a VCO. Properly designing source-degeneration capacitance can relieve this reduction and optimum capacitance is discussed in this paper. The chip is fabricated in 180 nm CMOS and has a chip area of 0.43 mm2. The measured oscillation frequency is from 2.22 GHz to 2.94 GHz (27.9 %) and the lowest phase noise is −122.5 dBc/Hz at 1MHz offset at 2.87 GHz. The core power dissipation is 3.6 mW from a supply voltage of 1.8 V and FOM of −186 dBc/Hz is achieved.