电荷耦合器件的三电平高容性负载时钟驱动器设计

Nishant Kumar, Shweta Kirkire, V. Patel, Sanjeev Mehta, A. R. Chowdhury
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引用次数: 0

摘要

大多数先进的线性和TDI(时间延迟集成)探测器的驱动要求在电压水平和容性负载驱动方面变得至关重要。这些探测器需要三电平双极时钟来驱动约7200pf的容性负载,其上升/下降时间约为~350ns,以提高电荷转移效率。没有现成的空间合格的三电平双极时钟驱动器可满足这些严格的要求。这就要求设计新的定制时钟驱动电子器件。因此,为了满足探测器的三电平双极时钟驱动要求,进行了基于分立晶体管的内部设计。本文讨论了该装置的设计细节、仿真和表征结果以及温度变化结果。
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Tri-level high capacitive load clock driver design for charge coupled devices
The drive requirements for most of the advanced linear and TDI [Time delay integration] detector is becoming critical with respect to voltage levels and capacitive load driving. These detectors require tri-level bipolar clocks for driving capacitive loads of the order of~7200 pF with fast rise/fall time of the order of ~350ns to improve the charge transfer efficiency. No off the shelf space qualified tri-level bipolar clock drivers are available to meet these stringent requirements. This calls for the design of new customized clock driver electronics. Hence discrete transistor based in-house design is carried out to cater to the tri-level bipolar clock driving requirements of detectors. This paper discusses the design details, simulation and characterization results and temperature variation results for the same.
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