{"title":"缓存一致共享内存超立方体多处理器","authors":"J. Ding, L. Bhuyan","doi":"10.1109/SPDP.1992.242701","DOIUrl":null,"url":null,"abstract":"The authors examine the feasibility of building cache coherent shared memory multiprocessor systems on hypercube. Various shared memory schemes are investigated and compared with each other. The schemes considered are based on memory coherence algorithms for distributed shared memory and cache coherence protocols for other shared memory architectures. It is concluded that efficient cache coherent architectures can be built using hypercubes.<<ETX>>","PeriodicalId":265469,"journal":{"name":"[1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Cache coherent shared memory hypercube multiprocessors\",\"authors\":\"J. Ding, L. Bhuyan\",\"doi\":\"10.1109/SPDP.1992.242701\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors examine the feasibility of building cache coherent shared memory multiprocessor systems on hypercube. Various shared memory schemes are investigated and compared with each other. The schemes considered are based on memory coherence algorithms for distributed shared memory and cache coherence protocols for other shared memory architectures. It is concluded that efficient cache coherent architectures can be built using hypercubes.<<ETX>>\",\"PeriodicalId\":265469,\"journal\":{\"name\":\"[1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPDP.1992.242701\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPDP.1992.242701","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors examine the feasibility of building cache coherent shared memory multiprocessor systems on hypercube. Various shared memory schemes are investigated and compared with each other. The schemes considered are based on memory coherence algorithms for distributed shared memory and cache coherence protocols for other shared memory architectures. It is concluded that efficient cache coherent architectures can be built using hypercubes.<>
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