Energy recovery clocking scheme and flip-flops for ultra low-energy applications

A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for future designs. We propose four novel energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. Based on the simulation results using TSMC 0.25 /spl mu/m CMOS process technology, at a frequency of 200 MHz, the proposed flip-flops exhibit more than 80% delay reduction, power reduction of up to 46%, and area reduction of up to 77%, as compared to the conventional energy recovery flip-flop. We implemented 1024 proposed energy recovery flip-flops through an H-tree clock network driven by a resonant clock-generator that generates a sinusoidal clock. Results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops.