92dB直流增益两级AB级全差分运算放大器

M. Shuaib
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引用次数: 0

摘要

设计数据转换器的主要挑战是高分辨率、高速度和低功耗。运算放大器(运放)是这种混合信号系统的核心构建模块,以克服这些问题。由于高分辨率与运算放大器的高直流增益和高速有关,因此需要单极响应和大单位增益频率。本文设计了输出级为AB级的两级运放,并在0.18um TSMC CMOS工艺下进行了仿真。本设计实现了高低频增益(92dB),良好的增益带宽产品(19.07MHz)和低功耗。为了稳定这个运放,使用的技术是米勒补偿,它具有补偿电容器($C_{m}$)和零零电阻($R_{Z}$),在本设计中,$R_{Z}$与PMOS晶体管一起实现了第二级的跨导($g_{m2}$),该跨导由电流设定为该级,以便将非主导极($f_{nd}$)推到更高的频率,以获得更好的增益带宽积(GBW)和良好的相位余量。
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92dB DC-Gain Two-Stage Class AB Fully-Differentail Op-amp
To design data converters main challenges are high resolution, high speed, and low power. Operational amplifiers (op-amps) are core building blocks in such mixed signal systems to overcome these issues. As high resolution is linked to op-amp's high dc gain and high speed demands single pole response and large unity gain frequency. This paper deals with design of two stage opamp with class AB as output stage and it has been simulated in 0.18um TSMC CMOS technology. This design achieves high low frequency gain(92dB), good gain bandwidth product(19.07MHz) and low power. To stabilize this op-amp techniques used are Miller compensation, which has compensation capacitor ($C_{m}$) and zero nulling resistor ($R_{Z}$), in this design $R_{Z}$ has been implemented with PMOS transistor along with transconductance ($g_{m2}$) of second stage, which is set by current is this stage in order to push non dominant pole ($f_{nd}$) to a higher frequency in order to get better gain band width product(GBW) and good phase margin.
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