{"title":"概率IP验证","authors":"R. Drechsler, B. Becker","doi":"10.1109/PACRIM.1999.799537","DOIUrl":null,"url":null,"abstract":"Modern VLSI CAD makes intensively use of core based design and integration of Intellectual Property (IP) to handle the IC design complexity. Several methods for IP integration in today's design flow have been proposed. In this paper we present a new model for verification of designs using IP. We make use of probabilistic algorithms to verify a circuit. Our model allows the IP owners and creators to keep all detailed information about the design, while the designer can probabilistically verify his design.","PeriodicalId":176763,"journal":{"name":"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Probabilistic IP verification\",\"authors\":\"R. Drechsler, B. Becker\",\"doi\":\"10.1109/PACRIM.1999.799537\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Modern VLSI CAD makes intensively use of core based design and integration of Intellectual Property (IP) to handle the IC design complexity. Several methods for IP integration in today's design flow have been proposed. In this paper we present a new model for verification of designs using IP. We make use of probabilistic algorithms to verify a circuit. Our model allows the IP owners and creators to keep all detailed information about the design, while the designer can probabilistically verify his design.\",\"PeriodicalId\":176763,\"journal\":{\"name\":\"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACRIM.1999.799537\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACRIM.1999.799537","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modern VLSI CAD makes intensively use of core based design and integration of Intellectual Property (IP) to handle the IC design complexity. Several methods for IP integration in today's design flow have been proposed. In this paper we present a new model for verification of designs using IP. We make use of probabilistic algorithms to verify a circuit. Our model allows the IP owners and creators to keep all detailed information about the design, while the designer can probabilistically verify his design.
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