VLSI功能测试合成的设计方法与实践

Proceedings of the 23rd International Conference on Information Technology Interfaces, 2001. ITI 2001. Pub Date : 2001-06-19 DOI:10.1109/ITI.2001.938056

J. Hudec

{"title":"VLSI功能测试合成的设计方法与实践","authors":"J. Hudec","doi":"10.1109/ITI.2001.938056","DOIUrl":null,"url":null,"abstract":"The paper presents a methodology overview for test synthesis of VLSI and ASIC systems using an automated process of VHDL synthesis simultaneously with Automatic Functional Test Generator (AFTG). The determination of the test efficiency of instruction mixes is discussed.","PeriodicalId":375405,"journal":{"name":"Proceedings of the 23rd International Conference on Information Technology Interfaces, 2001. ITI 2001.","volume":"353 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design methodology and practice of VLSI functional test synthesis\",\"authors\":\"J. Hudec\",\"doi\":\"10.1109/ITI.2001.938056\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a methodology overview for test synthesis of VLSI and ASIC systems using an automated process of VHDL synthesis simultaneously with Automatic Functional Test Generator (AFTG). The determination of the test efficiency of instruction mixes is discussed.\",\"PeriodicalId\":375405,\"journal\":{\"name\":\"Proceedings of the 23rd International Conference on Information Technology Interfaces, 2001. ITI 2001.\",\"volume\":\"353 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 23rd International Conference on Information Technology Interfaces, 2001. ITI 2001.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITI.2001.938056\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 23rd International Conference on Information Technology Interfaces, 2001. ITI 2001.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITI.2001.938056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文介绍了利用VHDL自动合成过程与自动功能测试生成器(AFTG)同时进行VLSI和ASIC系统测试合成的方法概述。讨论了指令混合测试效率的确定问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Design methodology and practice of VLSI functional test synthesis

The paper presents a methodology overview for test synthesis of VLSI and ASIC systems using an automated process of VHDL synthesis simultaneously with Automatic Functional Test Generator (AFTG). The determination of the test efficiency of instruction mixes is discussed.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the 23rd International Conference on Information Technology Interfaces, 2001. ITI 2001.

自引率

0.00%

发文量

期刊最新文献

Representing time-dependent information in Multidimensional XML Supplement to development of priority rule model in production management information system Modelling continuing professional development in an innovative context Conceptual learning of cardiac anomalies and surgeries Variable selection in discriminant analysis in the presence of outliers