A DC link switch-based common mode voltage reduction scheme in PWM inverter drives

Conventional pulse width modulation (PWM) methods for inverter application have the drawback of common mode voltage (CMV) issues, mainly due to the zero states when all the motor phases are clamped to the DC source or ground. A new three-phase voltage source inverter topology is proposed in this paper. The topology employs two switches on the DC link. A forced zero state (FZS) can be obtained when the DC-link switches are turned off. With the proposed topology, FZS space vector PWM (FZS-SVPWM) and FZS discontinuous PWM (FZS-DPWM) can be derived from conventional SVPWM and DPWM, respectively. The FZS-SVPWM and FZS-DPWM methods are effective in the CMV reduction aspect, whilst have the advantage of lower current ripple and acoustic noise than the existing reduced CMV PWM methods. Moreover, an FZS optimized PWM (FZSOPWM) is also proposed to improve performance. Simulation and experiment results validate the CMV and common mode current (CMC) reduction effect as well as the acoustic noise performance. The proposed topology is effective when both the low CMV/CMC and the low current ripple or acoustic noise are highly required.