{"title":"深亚微米时代精度、公差与补偿的关系","authors":"D. Hill, A. Domic","doi":"10.1109/ASIC.1997.616986","DOIUrl":null,"url":null,"abstract":"Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional \"over the wall\" methodology. Section 3 then proposes a \"limited loops\" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"On the relationship among accuracy, tolerance and compensation in the deep sub-micron era\",\"authors\":\"D. Hill, A. Domic\",\"doi\":\"10.1109/ASIC.1997.616986\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional \\\"over the wall\\\" methodology. Section 3 then proposes a \\\"limited loops\\\" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"352 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.616986\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.616986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On the relationship among accuracy, tolerance and compensation in the deep sub-micron era
Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional "over the wall" methodology. Section 3 then proposes a "limited loops" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.