{"title":"具有关联堆栈和虚拟寻址能力的模块化小型机","authors":"L.E.M. Warburton, J. S. Martin, D. Edwards","doi":"10.1049/IJ-CDT:19780004","DOIUrl":null,"url":null,"abstract":"The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1978-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Modular minicomputer with an associative stack and a virtual-addressing capability\",\"authors\":\"L.E.M. Warburton, J. S. Martin, D. Edwards\",\"doi\":\"10.1049/IJ-CDT:19780004\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.\",\"PeriodicalId\":344610,\"journal\":{\"name\":\"Iee Journal on Computers and Digital Techniques\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1978-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Iee Journal on Computers and Digital Techniques\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/IJ-CDT:19780004\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iee Journal on Computers and Digital Techniques","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/IJ-CDT:19780004","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modular minicomputer with an associative stack and a virtual-addressing capability
The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.