{"title":"基于32位嵌入式RISC处理器的SoC架构设计研究","authors":"Yuan Ying, Wu Wuchen, Hou Ligang, Geng Shuqin, Zhou Zhonghua, Liu Qi","doi":"10.1109/ISDEA.2012.431","DOIUrl":null,"url":null,"abstract":"As a important step in SoC design, good architecture design is the foundation to ensure the final structure to meet the design specifications. In paper, the minimal SoC system used for performance compare between basic architectures is defined, which is consisted of embedded processor, on chip bus, on chip memory and IP (GPIO). Then six SoC architecture based on 32 bit embedded RISC processor is studied, and comparison and analysis are discussed.","PeriodicalId":267532,"journal":{"name":"2012 Second International Conference on Intelligent System Design and Engineering Application","volume":"172 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The Study of SoC Architecture Design Based on 32-bit Embedded RISC Processor\",\"authors\":\"Yuan Ying, Wu Wuchen, Hou Ligang, Geng Shuqin, Zhou Zhonghua, Liu Qi\",\"doi\":\"10.1109/ISDEA.2012.431\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As a important step in SoC design, good architecture design is the foundation to ensure the final structure to meet the design specifications. In paper, the minimal SoC system used for performance compare between basic architectures is defined, which is consisted of embedded processor, on chip bus, on chip memory and IP (GPIO). Then six SoC architecture based on 32 bit embedded RISC processor is studied, and comparison and analysis are discussed.\",\"PeriodicalId\":267532,\"journal\":{\"name\":\"2012 Second International Conference on Intelligent System Design and Engineering Application\",\"volume\":\"172 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-01-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Second International Conference on Intelligent System Design and Engineering Application\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISDEA.2012.431\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Second International Conference on Intelligent System Design and Engineering Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISDEA.2012.431","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Study of SoC Architecture Design Based on 32-bit Embedded RISC Processor
As a important step in SoC design, good architecture design is the foundation to ensure the final structure to meet the design specifications. In paper, the minimal SoC system used for performance compare between basic architectures is defined, which is consisted of embedded processor, on chip bus, on chip memory and IP (GPIO). Then six SoC architecture based on 32 bit embedded RISC processor is studied, and comparison and analysis are discussed.
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