A Flexible Interleaved Memory Design for Generalized Low Conflict Memory Access

High bandwidth delivery of data to the processor(s) is critical for good perforniance in highly parallel computer systems. To increase memory throughput, many systems make use of interleaved parallel memory banks. An implementation must provide uniform throughput with little or no contention at the memory banks for a wide variety of algorithms and access patterns. This paper proposes an implementation for an interleaved memory system that exhibits extremely low contention for the memoiry banks during virtually all patterned accesses. It also has the advantage that, due to its programmability, it imposes few requirements on the configuration of the machines in which it is used. The hardware to implement the design is dliscussed along with address space considerations. A variant of this design is currently in use on the BBN TC2000 (tm) parallel computer.