非常快的LR解析

T. Pennello
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引用次数: 58

摘要

可以使LR解析器的运行速度比最好的表解释性LR解析器快6到10倍。与包含解析器的典型编译器的其余部分所需的时间相比,结果解析时间可以忽略不计。在类似于VAX 11/780的计算机上实现了每分钟50万行的解析速度,高于每分钟40,000行的解释速度。在Intel 80286上实现了每分钟24万行的速度,高于每分钟37,000行的解释速度。通过将解析器的有限状态控制转换成汇编语言实现了改进。状态成为代码存储器地址。当前输入符号驻留在寄存器中,寄存器常数比较的快速序列决定了下一个状态,这只是跳转到。解析器的下推堆栈直接在硬件堆栈上实现。堆栈包含代码内存地址,而不是传统的状态号。检查由解析器的终端和非终端转换引起的有向图的强连接组件,以确定在硬件不自动提供检查时需要解析时堆栈溢出检查代码的状态的一个典型的小子集。速度的提高是以牺牲空间为代价的:根据是否需要语法错误恢复,预计总表大小将增加2到4倍。
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Very fast LR parsing
LR parsers can be made to run 6 to 10 times as fast as the best table-interpretive LR parsers. The resulting parse time is negligible compared to the time required by the remainder of a typical compiler containing the parser. A parsing speed of 1/2 million lines per minute on a computer similar to a VAX 11/780 was achieved, up from an interpretive speed of 40,000 lines per minute. A speed of 240,000 lines per minute on an Intel 80286 was achieved, up from an interpretive speed of 37,000 lines per minute. The improvement is obtained by translating the parser's finite state control into assembly language. States become code memory addresses. The current input symbol resides in a register and a quick sequence of register-constant comparisons determines the next state, which is merely jumped to. The parser's push-down stack is implemented directly on a hardware stack. The stack contains code memory addresses rather than the traditional state numbers. The strongly-connected components of the directed graph induced by the parser's terminal and nonterminal transitions are examined to determine a typically small subset of the states that require parse-time stack-overflow-check code when hardware does not provide the check automatically. The increase in speed is at the expense of space: a factor of 2 to 4 increase in total table size can be expected, depending upon whether syntactic error recovery is required.
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