Cost-effective write disturbance mitigation techniques for advancing PCM density

Rapid technology scaling has enabled the integration of many cores into a single chip. Given this level of core integration, the requirements for a large and scalable main memory system will only grow. Current DRAM-based main memory systems face power and scalability issues when working at sub-micron scales. Phase Change Memory (PCM) has been proposed as one of the most promising technology candidates to replace or complement DRAM. However, scaling down cell sizes introduces significant thermal-based write disturbance challenges in PCM. Due to the heat generated for programming cells, neighboring cells may be disturbed, experiencing changes in their values. A naive solution is to increase inter-cell space, attempting to isolate cell programming and eliminating write disturbance, but this approach significantly reduces PCM density. In this paper, we propose two cost-effective solutions to reduce the probability of write disturbance. Our solutions come with few side-effects on other memory system metrics. The first technique is based on data encoding, and tries to reduce the number of vulnerable data patterns when writing data to main memory. The second technique detects vulnerable cells, and overwrites them if their occurrence is below a set threshold. The proposed techniques are general and can avoid much of the performance overhead introduced by write disturbance. Our proposed solutions can reduce the average number of writes by 49% over traditional schemes, while incurring minimal impact on PCM lifetime and energy consumption.