处理任意延迟相关性的快速统计时序分析

M. Orshansky, A. Bandyopadhyay
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引用次数: 116

摘要

描述了一种有效的统计时序分析算法,可以处理任意(空间和结构)延迟相关原因。该算法采用一种新的数学公式推导出整个电路延迟的累积分布函数。可以考虑栅极和导线延迟之间的空间和结构相关性。该算法可以处理由非高斯分布描述的节点延迟。由于具有任意分布的概率图的精确累积分布函数的解析计算是不可实现的,我们找到了真实累积分布的紧上界和下界。计算边界的一种有效算法是基于对包含N条确定性最长路径集的子图进行类似pert的单遍历。在一组ISCAS'85基准测试中验证了该算法的效率和准确性。在所有基准中,准确分布与下限之间的平均均方根误差为0.7%,第95百分位的平均最大误差为0.6%。计算最大基准的边界需要39秒。
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Fast statistical timing analysis handling arbitrary delay correlations
An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire cumulative distribution function of the circuit delay using a new mathematical formulation. Spatial as well as structural correlations between gate and wire delays can be taken into account. The algorithm can handle node delays described by non-Gaussian distributions. Because the analytical computation of an exact cumulative distribution function for a probabilistic graph with arbitrary distributions is infeasible, we find tight upper and lower bounds on the true cumulative distribution. An efficient algorithm to compute the bounds is based on a PERT-like single traversal of the sub-graph containing the set of N deterministically longest paths. The efficiency and accuracy of the algorithm is demonstrated on a set of ISCAS'85 benchmarks. Across all the benchmarks, the average rms error between the exact distribution and lower bound is 0.7%, and the average maximum error at 95th percentile is 0.6%. The computation of bounds for the largest benchmark takes 39 seconds.
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