提高锁相环拉入能力的一种简单技术

K. Hiroshige
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引用次数: 7

摘要

本文提出了一种提高锁相环拉入能力的简单方法。这种技术称为派生速率抑制或DRR,与使用外部AFC环路的技术在实现和设计原理上的简单性不同,尽管最终结果是相同的。如果,通常情况下,一个相干检测器伴随着锁相环,DRR技术的实现只需要增加一个开关。开关逻辑是由于对锁相环的非线性方程及其在相平面上的解的肤浅考虑而产生的。在锁定后,开关不会影响环路的正常行为。计算机研究结果表明,对于以下配置,可以实现改进:1)比例加积分控制。2)比例加不完全积分控制。当初始频率误差为线性化锁相环固有频率的5倍时,拉入时间的改善是原来的2倍。当初始频率误差为锁相环固有频率的十倍时,拉入时间的改善是十倍。
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A Simple Technique for Improving the Pull-in Capability of Phase-Lock Loops
This paper presents a simple technique for improving the pull-in capability of phase-lock loops. This technique, called derived rate rejection or DRR, differs from those which use an external AFC loop in simplicity of implementation and design rationale, although the end result is the same. If, as is usually the case, a coherent detector accompanies the phase-lock loop, the implementation of the DRR technique requires only the addition of a switch. The switching logic results from a superficial consideration of the nonlinear equation for the phase-lock loop and its solution in the phase plane. The switch does not affect the normal behavior of the loop after lock has been attained. Results of computer studies show the improvement realizable for the following configurations: 1) Proportional-plus-integral control. 2) Proportional-plus-imperfect integral control. For an initial frequency error of five times the linearized phase lock-loop natural frequency, the improvement in pull-in time is a factor of two. For an initial frequency error of ten times the phase-lock loop natural frequency, the improvement in pull-in time is a factor of ten.
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