{"title":"开发用于道路交通监控的智能摄像头","authors":"Bei Na Wei, Yu Shi, G. Ye, Jie Xu","doi":"10.1109/MMSP.2008.4665188","DOIUrl":null,"url":null,"abstract":"Smart camera system design and implementation is a challenging task due to the constant need to perform computationally demanding image processing tasks with the limited resource constraints of embedded systems. This paper presents the hardware and software co-design and implementation of the first stage of TraffiCam, an FPGA based smart camera prototype for traffic surveillance at intersections, consisting of a CMOS image sensor capture device and FPGA main video processor. In particular, creative solutions for balancing gate array utilization, memory and computation time are presented for the initial stage of Harris keypoint detection with discussions on the algorithm implementation conversions between PC-based to FPGA based platforms. Preliminary results show satisfactory real-time tracking and estimation performance.","PeriodicalId":402287,"journal":{"name":"2008 IEEE 10th Workshop on Multimedia Signal Processing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Developing a smart camera for road traffic surveillance\",\"authors\":\"Bei Na Wei, Yu Shi, G. Ye, Jie Xu\",\"doi\":\"10.1109/MMSP.2008.4665188\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Smart camera system design and implementation is a challenging task due to the constant need to perform computationally demanding image processing tasks with the limited resource constraints of embedded systems. This paper presents the hardware and software co-design and implementation of the first stage of TraffiCam, an FPGA based smart camera prototype for traffic surveillance at intersections, consisting of a CMOS image sensor capture device and FPGA main video processor. In particular, creative solutions for balancing gate array utilization, memory and computation time are presented for the initial stage of Harris keypoint detection with discussions on the algorithm implementation conversions between PC-based to FPGA based platforms. Preliminary results show satisfactory real-time tracking and estimation performance.\",\"PeriodicalId\":402287,\"journal\":{\"name\":\"2008 IEEE 10th Workshop on Multimedia Signal Processing\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE 10th Workshop on Multimedia Signal Processing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MMSP.2008.4665188\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE 10th Workshop on Multimedia Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MMSP.2008.4665188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Developing a smart camera for road traffic surveillance
Smart camera system design and implementation is a challenging task due to the constant need to perform computationally demanding image processing tasks with the limited resource constraints of embedded systems. This paper presents the hardware and software co-design and implementation of the first stage of TraffiCam, an FPGA based smart camera prototype for traffic surveillance at intersections, consisting of a CMOS image sensor capture device and FPGA main video processor. In particular, creative solutions for balancing gate array utilization, memory and computation time are presented for the initial stage of Harris keypoint detection with discussions on the algorithm implementation conversions between PC-based to FPGA based platforms. Preliminary results show satisfactory real-time tracking and estimation performance.