Daeyeal Lee, I. Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, I. Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yongdeok Cho, Kyung-Min Kang, Sanghoon Joo, Jin-Young Chun, Jung-No Im, S. Kwon, Seo-Hyeon Ham, Ansoo Park, Jaemin Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, B. Jeon, Kihwan Choi, Jin-Man Han, K. Kyung, Y. Lim, Young-Hyun Jun
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A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology
The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].
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