An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology

In this paper, a low-leakage PMOS based transient clamp with a thyristor as a delay element in 65 nm general-purpose (GP) CMOS technology is presented. Simulation results show that the proposed clamp is capable of protecting the circuit core against ±1.5 kV HBM and ±125 V CDM ESD stress by limiting the voltage across it to less than 5 V. The proposed clamp was characterized over PVT conditions with 2200 different combinations to investigate the selectivity to power-on ramp rates. Extensive analysis and measurements demonstrate that the clamp is robust against false triggering and transient induced latch-up. Measurement results show that the clamp is capable of handling 3.82 A, while its leakage is only 494 pA at room temperature. HBM and CDM measurement results show that the proposed clamp passed +3.25 kV and −1.75 kV HBM stresses and +800 V and −550 V CDM stresses.