{"title":"采用45nm技术的超低面积全摆幅输出3T XNOR栅极","authors":"S. Jayanth, M. Poorvi, M. Sunil","doi":"10.1109/ICACCS.2016.7586366","DOIUrl":null,"url":null,"abstract":"In this research paper we are presenting a new idea of a 3 transistor Exclusive NOR (XNOR) gate that produces low power and high performance with more noise immunity. The main aim of this research is to achieve maximum output voltage swing with improved delay, power and power delay product compared to the previous designs. The pre-simulation of the design is performed using Cadence EDA tool of 45nm technology.","PeriodicalId":176803,"journal":{"name":"2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An ultra-low area and full-swing output 3T XNOR gate using 45nm technology\",\"authors\":\"S. Jayanth, M. Poorvi, M. Sunil\",\"doi\":\"10.1109/ICACCS.2016.7586366\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this research paper we are presenting a new idea of a 3 transistor Exclusive NOR (XNOR) gate that produces low power and high performance with more noise immunity. The main aim of this research is to achieve maximum output voltage swing with improved delay, power and power delay product compared to the previous designs. The pre-simulation of the design is performed using Cadence EDA tool of 45nm technology.\",\"PeriodicalId\":176803,\"journal\":{\"name\":\"2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS)\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICACCS.2016.7586366\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICACCS.2016.7586366","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An ultra-low area and full-swing output 3T XNOR gate using 45nm technology
In this research paper we are presenting a new idea of a 3 transistor Exclusive NOR (XNOR) gate that produces low power and high performance with more noise immunity. The main aim of this research is to achieve maximum output voltage swing with improved delay, power and power delay product compared to the previous designs. The pre-simulation of the design is performed using Cadence EDA tool of 45nm technology.
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