T. S. Rani, Avireni Srinivasulu, C. Ravariu, B. Appasani
{"title":"低功耗,高性能PMOS偏置感测放大器","authors":"T. S. Rani, Avireni Srinivasulu, C. Ravariu, B. Appasani","doi":"10.1109/ATEE52255.2021.9425279","DOIUrl":null,"url":null,"abstract":"Sense amplifiers plays a significant role in terms of its recital, functionality and reliability of the memory circuits. In this paper two new circuits have been proposed. The proposed circuit is PMOS biased sense amplifier, which provides very high output impedance and has reduced sense delay and power dissipation. As such, the proposed circuit performs the identical operations as that of conventional circuits but with the reduced the sense delay and power consumption. The suggested sense amplifiers overall performance have been simulated and examined using Cadence virtuoso with gpdk 180 nm library parameters.","PeriodicalId":359645,"journal":{"name":"2021 12th International Symposium on Advanced Topics in Electrical Engineering (ATEE)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Low Power, High Performance PMOS Biased Sense Amplifier\",\"authors\":\"T. S. Rani, Avireni Srinivasulu, C. Ravariu, B. Appasani\",\"doi\":\"10.1109/ATEE52255.2021.9425279\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Sense amplifiers plays a significant role in terms of its recital, functionality and reliability of the memory circuits. In this paper two new circuits have been proposed. The proposed circuit is PMOS biased sense amplifier, which provides very high output impedance and has reduced sense delay and power dissipation. As such, the proposed circuit performs the identical operations as that of conventional circuits but with the reduced the sense delay and power consumption. The suggested sense amplifiers overall performance have been simulated and examined using Cadence virtuoso with gpdk 180 nm library parameters.\",\"PeriodicalId\":359645,\"journal\":{\"name\":\"2021 12th International Symposium on Advanced Topics in Electrical Engineering (ATEE)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-03-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 12th International Symposium on Advanced Topics in Electrical Engineering (ATEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATEE52255.2021.9425279\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 12th International Symposium on Advanced Topics in Electrical Engineering (ATEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATEE52255.2021.9425279","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low Power, High Performance PMOS Biased Sense Amplifier
Sense amplifiers plays a significant role in terms of its recital, functionality and reliability of the memory circuits. In this paper two new circuits have been proposed. The proposed circuit is PMOS biased sense amplifier, which provides very high output impedance and has reduced sense delay and power dissipation. As such, the proposed circuit performs the identical operations as that of conventional circuits but with the reduced the sense delay and power consumption. The suggested sense amplifiers overall performance have been simulated and examined using Cadence virtuoso with gpdk 180 nm library parameters.