Area efficient fused floating point three term adder

Addition is the most frequently used operation in many algorithms and applications. The limited precision in the floating point representation requires rounding and basically makes the FP addition sensitive to the operand order. When adding multiple FP operands using a network of 2-input floating point adders, the error in the final result can be significant. Besides, the use of several two input floating point adders on a circuit may result in long delays that could be avoided with an integrated solution. The fused three-term floating-point adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders. Floating-point operations require complex processes such as alignment, normalization and rounding, which increases the area, power consumption and latency. In order to further improve the performance of the three-term adder, several optimization techniques are applied including a new exponent compare and significand alignment, dual-reduction, early normalization, three-input leading zero anticipation, compound addition/rounding and pipelining. The proposed design is implemented for single precision. This paper is trying to demonstrate a novel design for fused floating point three term adder.