{"title":"PET数字符合检测中的最佳带宽使用","authors":"J. Young, M. Casey, D. Newport","doi":"10.1109/NSSMIC.1993.701835","DOIUrl":null,"url":null,"abstract":"In positron emission tomographs (PET), the ratio of time coincident events to single events is less than one out of twenty. A significant reduction in the bandwidth necessary to transmit the coincident events to a histogramming circuit can be achieved by using this fact. Since the coincident events occur randomly, there is a finite chance that no coincident events occur within a clock cycle. We present an architecture that uses the vacant clock cycles to transmit any extra events that occur during non-zero clock cycles. An analysis of this architecture along with a Monte Carlo simulation show that a reduction in complexity can be achieved while maintaining virtually no event loss at coincidence rates near channel saturation. This architecture has been implemented in a VLSI gate array and is presented in the paper.","PeriodicalId":287813,"journal":{"name":"1993 IEEE Conference Record Nuclear Science Symposium and Medical Imaging Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Optimum Bandwidth Usage In Digital Coincidence Detection For PET\",\"authors\":\"J. Young, M. Casey, D. Newport\",\"doi\":\"10.1109/NSSMIC.1993.701835\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In positron emission tomographs (PET), the ratio of time coincident events to single events is less than one out of twenty. A significant reduction in the bandwidth necessary to transmit the coincident events to a histogramming circuit can be achieved by using this fact. Since the coincident events occur randomly, there is a finite chance that no coincident events occur within a clock cycle. We present an architecture that uses the vacant clock cycles to transmit any extra events that occur during non-zero clock cycles. An analysis of this architecture along with a Monte Carlo simulation show that a reduction in complexity can be achieved while maintaining virtually no event loss at coincidence rates near channel saturation. This architecture has been implemented in a VLSI gate array and is presented in the paper.\",\"PeriodicalId\":287813,\"journal\":{\"name\":\"1993 IEEE Conference Record Nuclear Science Symposium and Medical Imaging Conference\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1993 IEEE Conference Record Nuclear Science Symposium and Medical Imaging Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NSSMIC.1993.701835\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1993 IEEE Conference Record Nuclear Science Symposium and Medical Imaging Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NSSMIC.1993.701835","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimum Bandwidth Usage In Digital Coincidence Detection For PET
In positron emission tomographs (PET), the ratio of time coincident events to single events is less than one out of twenty. A significant reduction in the bandwidth necessary to transmit the coincident events to a histogramming circuit can be achieved by using this fact. Since the coincident events occur randomly, there is a finite chance that no coincident events occur within a clock cycle. We present an architecture that uses the vacant clock cycles to transmit any extra events that occur during non-zero clock cycles. An analysis of this architecture along with a Monte Carlo simulation show that a reduction in complexity can be achieved while maintaining virtually no event loss at coincidence rates near channel saturation. This architecture has been implemented in a VLSI gate array and is presented in the paper.