一种测量微处理器电源阻抗的方法

IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI:10.1109/EPEP.2001.967648

G. Taylor, C. Deutschle, T. Arabi, B. Owens

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引用次数: 6

摘要

介绍了一种计算高功率CMOS集成电路模内相对电源阻抗随频率变化的方法。这种方法使用通常存在于微处理器中的电源电流变化来刺激供电网络，改变处理器的时钟速率以获得多次测量。利用该技术测量了0.18 /spl μ m微处理器的电源阻抗与频率的关系，并与简单的集总电路模型进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An approach to measuring power supply impedance of microprocessors

A technique to calculate the relative on die power supply impedance of high power CMOS integrated circuits as a function of frequency is described. This approach uses the power supply current variation that is normally present in a microprocessor to stimulate the supply network, varying the clock rate of the processor in order to obtain multiple measurements. Using this technique the power supply impedance vs. frequency of a 0.18 /spl mu/m microprocessor was measured and compared to a simple lumped circuit model.

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IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)

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