{"title":"一种用于集成电路的内禀区域阵列pad路由器","authors":"C. Tan, D. Bouldin, P. Dehkordi","doi":"10.1109/ASIC.1997.617018","DOIUrl":null,"url":null,"abstract":"Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design implementation of this technique and show the results of applying this router on designs requiring 112, 298, 414 and 485 I/Os.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"An intrinsic area-array pad router for ICs\",\"authors\":\"C. Tan, D. Bouldin, P. Dehkordi\",\"doi\":\"10.1109/ASIC.1997.617018\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design implementation of this technique and show the results of applying this router on designs requiring 112, 298, 414 and 485 I/Os.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617018\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Arranging I/Os in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/Os than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. In this paper we describe the development of a new area-array pad router which differs from other approaches in that no additional metal layer is added (unless needed) and no redistribution is required. We describe the design implementation of this technique and show the results of applying this router on designs requiring 112, 298, 414 and 485 I/Os.
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