S. Dogimont, M. Gumm, F. Mombers, D. Mlynek, A. Torielli
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Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture
In this paper, the problem of defining a high performance control structure for a parallel motion estimation architecture for MPEG2 coding is addressed. Various design and architecture choices are discussed and the final architecture is described. It represents a combined MIMD-SIMD approach which is based on a small but efficient ASIP with subword parallelism.
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