Asynchronous 2-D discrete cosine transform core processor

To lend additional insight into the reality of self-timed design, this paper proposes a large-scale, application specific, asynchronous design-a CCITT compatible asynchronous DCT/IDCT processor. The prototype DCT/IDCT processor uses two-phase transition signaling and a bounded delay approach to implement a modified version of Sutherland's micropipeline. The layout of the core processor was designed using standard cell and custom techniques to integrate 150,000 transistors in a 2 /spl mu/ SCMOS technology. This investigation presents the prototype DCT/IDCT processor design and the resulting measures of speed, power, and area.