A 40nm area-efficient Effective-bit-combination-based DNN accelerator with the reconfigurable multiplier

Deep neural networks (DNNs) are widely used in various tasks, such as image classification and speech recognition. When deploying DNN to the edge device, the inputs and weights are usually quantized. And there are obvious patterns in the data distribution. Most data have numerous redundant bits, which reduce the utilization rate of computation resources. We proposed an area-efficient DNN accelerator with an effective bit combination mechanism and a reconfigurable multiplier. Based on the modified Baugh-Wooly multiplier, we proposed a multiplier that can process two 4-bit multiplication operations in one cycle, consuming only 1.57 times the area and 2.31 times the power consumption of a traditional multiplier. Based on the data distribution in DNN, we propose a gating approach for the weights of 0, -1, and 1, resulting in a 34.96% reduction in power consumption. The normalized area efficiency of the proposed DNN accelerator using 40nm CMOS technology is 1.11 to 4.90 times higher than previous works [4] - [7].