High-throughput dual-shift stochastic-detection quasi-cyclic LDPC decoder

Driven by its renowned near-capacity performance over a wide spectrum of channels, the capitalization of quasi-cyclic low-density parity-check (QC-LDPC) codes is irrefutably the focal point of research and solution to virtually all communication systems of the next generation. Steered towards non-volatile memory (NVM) storage applications, we introduce a modernistic approach to LDPC decoding in this paper, known as the dual-shift stochastic-detection (DSSD). Weaving two novel ideas: dual-shift cyclic generation and stochastic-detection of local minima, our proposed DSSD decoder achieves throughput gains (~ 300%) by minimizing its overall computational delay and maximizing its operational frequency. Along with the amalgamation of our spearheading mirror-paradigm, the DSSD QC-LDPC decoder acquires yet another dimension of gain in throughput while relinquishing a cluster of its address generation counters, which elicits a wide expanse for its application.