实时收缩排序阵列的并发错误检测和校正

Sheng-Chiech Liang, S. Kuo
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引用次数: 15

摘要

提出了一种高通量VLSI排序阵列的在线错误检测与校正方法。错误模型在排序元素级别定义,并且考虑了功能错误和由故障元素产生的数据错误。利用排序阵列的固有特性和作者发现的特殊特性,检测和修正了功能误差。开发了编码技术和在线故障诊断程序来定位数据错误。所有的检查器都被设计为完全自检,因此排序阵列具有很高的可靠性。本设计采用两级流水线,效率高,适合实时应用。对于典型的数组大小,硬件开销并不大,时间损失只有三个时钟周期。该结构非常规则,因此对于VLSI或WSI实现非常有吸引力。
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Concurrent error detection and correction in real-time systolic sorting arrays
An approach to online error detection and correction for high-throughput VLSI sorting arrays is presented. The error model is defined at the sorting element level, and both functional errors and data errors generated by a faulty element are considered. The functional errors are detected and corrected by exploiting inherent properties of the sorting array, as well as special properties discovered by the authors. Coding techniques and an online fault diagnosis procedure are developed to locate data errors. All the checkers are designed to be totally self-checking, and hence the sorting array is highly reliable. Two-level pipelining is employed in this design, making it very efficient and suitable for real-time application. The hardware overhead is not significant for typical array sizes, and the time penalty is only three clock cycles. The structure is very regular and therefore very attractive for VLSI or WSI implementation.<>
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