Throughput Efficient Parallel Implementation of SPIHT Algorithm

We present a throughput efficient FPGA implementation of the 'Set Partitioning in Hierarchical Trees' (SPIHT) algorithm for compression of images. The SPIHT uses inherent redundancy among wavelet coefficients and suited for both gray and color images. The SPIHT algorithm uses dynamic data structures which hinders hardware realization. In our FPGA implementation we have modified basic SPIHT in two ways, one by using static (fixed) mappings which represent significant information and the other by interchanging the sorting and refinement passes. A hardware realization is done in a Xilinx XC2S30 device. Significant compression ratio and throughput is obtained for a sample image of size 128 times 128 pixels.