{"title":"HSA环境下边缘检测的实现","authors":"S. Prongnuch, T. Wiangtong","doi":"10.1109/IEECON.2017.8075811","DOIUrl":null,"url":null,"abstract":"This paper presents the implementation of image edge detection on Heterogeneous System Architecture (HSA). HSA which includes ARM processor, Coprocessor and FPGA are compared with x64 CPU in terms of performance and power consumption. The experimental results show that although the best execution time is from x64 CPU, HSA has 50 times more energy efficiency. Also, HSA can exploit coprocessors and reconfigurable hardware to reduce processing time and it can achieve 1.3x speedup when process an image with the size of 512×512 pixels.","PeriodicalId":196081,"journal":{"name":"2017 International Electrical Engineering Congress (iEECON)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The implementation of edge detection on HSA environment\",\"authors\":\"S. Prongnuch, T. Wiangtong\",\"doi\":\"10.1109/IEECON.2017.8075811\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the implementation of image edge detection on Heterogeneous System Architecture (HSA). HSA which includes ARM processor, Coprocessor and FPGA are compared with x64 CPU in terms of performance and power consumption. The experimental results show that although the best execution time is from x64 CPU, HSA has 50 times more energy efficiency. Also, HSA can exploit coprocessors and reconfigurable hardware to reduce processing time and it can achieve 1.3x speedup when process an image with the size of 512×512 pixels.\",\"PeriodicalId\":196081,\"journal\":{\"name\":\"2017 International Electrical Engineering Congress (iEECON)\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-03-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Electrical Engineering Congress (iEECON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEECON.2017.8075811\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Electrical Engineering Congress (iEECON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEECON.2017.8075811","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The implementation of edge detection on HSA environment
This paper presents the implementation of image edge detection on Heterogeneous System Architecture (HSA). HSA which includes ARM processor, Coprocessor and FPGA are compared with x64 CPU in terms of performance and power consumption. The experimental results show that although the best execution time is from x64 CPU, HSA has 50 times more energy efficiency. Also, HSA can exploit coprocessors and reconfigurable hardware to reduce processing time and it can achieve 1.3x speedup when process an image with the size of 512×512 pixels.