A Novel SLM-Based Virtual FPGA Overlay Architecture

To implement virtual field-programmable gate array (vFPGA) layers on physical devices, FPGA overlay technologies have been introduced to provide inter-FPGA bitstream compatibility. Conventional LUT-based vFPGA overlay architectures have very large resource overheads because LUT resource requirements increase as O(2k) with an increasing number of inputs, k. In this paper, we propose a novel SLM-based vFPGA overlay architectures that employ our previously proposed scalable logic module (SLM) as a logic cell. SLMs can cover most frequently used logics with far fewer hardware resources than LUTs. Evaluation results show that a 6-input SLM-based vFPGA can reduce LUT and flip-flop resource usage by up to 21% and 21% on an Artix-7 FPGA, on a Kintex-7 FPGA, and on a Kintex UltraScale+ FPGA respectively, as compared to a LUT-based vFPGA of the same input size. Similarly, a 7-input SLM-based vFPGA can reduce LUT and flip-flop resource usage by up to 32% and 35% on an Artix-7 FPGA, 30% and 35% on a Kintex-7 FPGA, and 30% and 35% on a Kintex UltraScale+ FPGA respectively, as compared to a LUT-based vFPGA of the same input size. Delay results of SLM-based vFPGA overlay architectures are almost the same with the comparison of LUTbased vFPGA overlay architectures.