{"title":"未知缓存大小的协同缓存","authors":"Xiaoming Gu","doi":"10.1109/PACT.2011.50","DOIUrl":null,"url":null,"abstract":"A number of hardware systems have been built or proposed to provide an interface for software to influence cache management. The combined software-hardware solution is called collaborative caching. Our previous work showed that in theory collaborative caching with LRU and MRU may enable a program to manage cache optimally. In this work we first present a prioritized LRU model. For each memory access, a program specifies a priority, the target cache position for the accessed datum, for all cache sizes. We have proved that the prioritized LRU holds inclusion property. Alternatively, we describe a dynamic cache control scheme based on the associated priority. The limitation of knowing cache size in our LRU-MRU collaborative caching work is removed.","PeriodicalId":106423,"journal":{"name":"2011 International Conference on Parallel Architectures and Compilation Techniques","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Collaborative Caching for Unknown Cache Sizes\",\"authors\":\"Xiaoming Gu\",\"doi\":\"10.1109/PACT.2011.50\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A number of hardware systems have been built or proposed to provide an interface for software to influence cache management. The combined software-hardware solution is called collaborative caching. Our previous work showed that in theory collaborative caching with LRU and MRU may enable a program to manage cache optimally. In this work we first present a prioritized LRU model. For each memory access, a program specifies a priority, the target cache position for the accessed datum, for all cache sizes. We have proved that the prioritized LRU holds inclusion property. Alternatively, we describe a dynamic cache control scheme based on the associated priority. The limitation of knowing cache size in our LRU-MRU collaborative caching work is removed.\",\"PeriodicalId\":106423,\"journal\":{\"name\":\"2011 International Conference on Parallel Architectures and Compilation Techniques\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Conference on Parallel Architectures and Compilation Techniques\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACT.2011.50\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Parallel Architectures and Compilation Techniques","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACT.2011.50","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A number of hardware systems have been built or proposed to provide an interface for software to influence cache management. The combined software-hardware solution is called collaborative caching. Our previous work showed that in theory collaborative caching with LRU and MRU may enable a program to manage cache optimally. In this work we first present a prioritized LRU model. For each memory access, a program specifies a priority, the target cache position for the accessed datum, for all cache sizes. We have proved that the prioritized LRU holds inclusion property. Alternatively, we describe a dynamic cache control scheme based on the associated priority. The limitation of knowing cache size in our LRU-MRU collaborative caching work is removed.