{"title":"低功耗随机脉冲编码系统构件的合成","authors":"S. Naess, T. Lande","doi":"10.1109/ASIC.1997.617015","DOIUrl":null,"url":null,"abstract":"This paper presents an approach for device-level synthesis of building blocks for stochastic pulse coded (SPC) systems. SPC systems have design properties which are quite different from traditional analog systems, and require new strategies to solve the problems efficiently. The strategies and algorithms solving the problems are described. The feasibility of the methods is demonstrated through the device-level synthesis of a large building block.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Synthesis of building blocks for low-power stochastic pulse coded systems\",\"authors\":\"S. Naess, T. Lande\",\"doi\":\"10.1109/ASIC.1997.617015\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an approach for device-level synthesis of building blocks for stochastic pulse coded (SPC) systems. SPC systems have design properties which are quite different from traditional analog systems, and require new strategies to solve the problems efficiently. The strategies and algorithms solving the problems are described. The feasibility of the methods is demonstrated through the device-level synthesis of a large building block.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617015\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Synthesis of building blocks for low-power stochastic pulse coded systems
This paper presents an approach for device-level synthesis of building blocks for stochastic pulse coded (SPC) systems. SPC systems have design properties which are quite different from traditional analog systems, and require new strategies to solve the problems efficiently. The strategies and algorithms solving the problems are described. The feasibility of the methods is demonstrated through the device-level synthesis of a large building block.