迈向单主机多gpu系统

Ming-Hung Chen, I. Chung, B. Abali, P. Crumley
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引用次数: 1

摘要

随着深度学习和大数据分析等计算密集型任务利用基于GPU的加速器,互连链路可能成为瓶颈。在本文中,我们研究了随着单个主机上的加速器数量的增加,多加速器系统即将出现的性能瓶颈。我们测量了主机PCIe结构来测量数据传输,并将其与软件工具的测量结果进行了比较。它显示了数据传输(P2P)如何帮助避免互连链路上的瓶颈,但由于控制消息,多gpu性能并没有像预期的那样扩展。我们量化了主机控制消息的影响,并提出了补救可伸缩性瓶颈的建议。我们还在Lulesh上实施了所提出的策略来验证这一概念。结果表明,该策略可节省59.86%的内核时间成本和13.32%的PCIe H2D负载。
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Towards a Single-Host Many-GPU System
As computation-intensive tasks such as deep learning and big data analysis take advantage of GPU based accelerators, the interconnection links may become a bottleneck. In this paper, we investigate the upcoming performance bottleneck of multi-accelerator systems, as the number of accelerators equipped with single host grows. We instrumented the host PCIe fabric to measure the data transfer and compared it with the measurements from the software tool. It shows how the data transfer (P2P) helps to avoid the bottleneck on the interconnection links, but multi-GPU performance does not scale up as expected due to the control messages. We quantify the impact of host control messages with suggestions to remedy scalability bottlenecks. We also implement the proposed strategy on Lulesh to validate the concept. The result shows our strategy can save 59.86% time cost of the kernel and 13.32% PCIe H2D payload.
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