{"title":"减少平移旁缓冲有功功率","authors":"L. Clark, Byungwoo Choi, M. Wilkerson","doi":"10.1145/871506.871512","DOIUrl":null,"url":null,"abstract":"Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18 /spl mu/m process technology demonstrate 42% power savings. Circuit implementations, as well as. architectural simulations demonstrating applicability to typical instruction mixes are shown.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"Reducing translation lookaside buffer active power\",\"authors\":\"L. Clark, Byungwoo Choi, M. Wilkerson\",\"doi\":\"10.1145/871506.871512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18 /spl mu/m process technology demonstrate 42% power savings. Circuit implementations, as well as. architectural simulations demonstrating applicability to typical instruction mixes are shown.\",\"PeriodicalId\":355883,\"journal\":{\"name\":\"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.\",\"volume\":\"84 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-08-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/871506.871512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/871506.871512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reducing translation lookaside buffer active power
Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18 /spl mu/m process technology demonstrate 42% power savings. Circuit implementations, as well as. architectural simulations demonstrating applicability to typical instruction mixes are shown.
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