{"title":"多核soc的按需存储器子系统","authors":"Po-Tsang Huang, Yu-ning Chang, W. Hwang","doi":"10.1109/SOCC.2011.6085132","DOIUrl":null,"url":null,"abstract":"For heterogeneous multi-core SoCs, the increasing demand of the memory capacity and bandwidth becomes a critical design challenge. In this paper, an on-demand memory sub-system is presented to efficiently control the memory access and memory resource allocation using adaptively allocated cache memory. The proposed adaptively allocated cache memory can dynamically assign a variable number of SRAM banks for process elements (PEs) to optimize the utilization of the centralized on-chip cache. In a wireless video entertainment system, a 7.13% execution time reduction and 10.53% energy reduction of memories can be achieved using the adaptively allocated cache memory.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"On-demand memory sub-system for multi-core SoCs\",\"authors\":\"Po-Tsang Huang, Yu-ning Chang, W. Hwang\",\"doi\":\"10.1109/SOCC.2011.6085132\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For heterogeneous multi-core SoCs, the increasing demand of the memory capacity and bandwidth becomes a critical design challenge. In this paper, an on-demand memory sub-system is presented to efficiently control the memory access and memory resource allocation using adaptively allocated cache memory. The proposed adaptively allocated cache memory can dynamically assign a variable number of SRAM banks for process elements (PEs) to optimize the utilization of the centralized on-chip cache. In a wireless video entertainment system, a 7.13% execution time reduction and 10.53% energy reduction of memories can be achieved using the adaptively allocated cache memory.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085132\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085132","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
For heterogeneous multi-core SoCs, the increasing demand of the memory capacity and bandwidth becomes a critical design challenge. In this paper, an on-demand memory sub-system is presented to efficiently control the memory access and memory resource allocation using adaptively allocated cache memory. The proposed adaptively allocated cache memory can dynamically assign a variable number of SRAM banks for process elements (PEs) to optimize the utilization of the centralized on-chip cache. In a wireless video entertainment system, a 7.13% execution time reduction and 10.53% energy reduction of memories can be achieved using the adaptively allocated cache memory.