{"title":"快速H.264 CAVLC解码器体系结构及其FPGA实现","authors":"T. George, N. Malmurugan","doi":"10.1109/IIH-MSP.2007.291","DOIUrl":null,"url":null,"abstract":"In this paper, we present a fast architecture of realtime CAVLC decoder (CAVLD) implemented in a FPGA. The real-time performance is achieved by exploring the pipelining possibilities between the sub- modules and multi sub-symbol decoding. The implemented fast CAVLD architecture, when integrated with H264 decoder was capable of parsing at 30 fps for 1080 p streams for an encoded bit stream at a bit rate of 200 Mbps to achieve the real-time performance, while the clock is operated at 74.25 MHz. The result numbers of ALUs are 3266 and the critical path is within 10.5 ns.","PeriodicalId":385132,"journal":{"name":"Third International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"The Architecture of Fast H.264 CAVLC Decoder and its FPGA Implementation\",\"authors\":\"T. George, N. Malmurugan\",\"doi\":\"10.1109/IIH-MSP.2007.291\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a fast architecture of realtime CAVLC decoder (CAVLD) implemented in a FPGA. The real-time performance is achieved by exploring the pipelining possibilities between the sub- modules and multi sub-symbol decoding. The implemented fast CAVLD architecture, when integrated with H264 decoder was capable of parsing at 30 fps for 1080 p streams for an encoded bit stream at a bit rate of 200 Mbps to achieve the real-time performance, while the clock is operated at 74.25 MHz. The result numbers of ALUs are 3266 and the critical path is within 10.5 ns.\",\"PeriodicalId\":385132,\"journal\":{\"name\":\"Third International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IIH-MSP.2007.291\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIH-MSP.2007.291","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Architecture of Fast H.264 CAVLC Decoder and its FPGA Implementation
In this paper, we present a fast architecture of realtime CAVLC decoder (CAVLD) implemented in a FPGA. The real-time performance is achieved by exploring the pipelining possibilities between the sub- modules and multi sub-symbol decoding. The implemented fast CAVLD architecture, when integrated with H264 decoder was capable of parsing at 30 fps for 1080 p streams for an encoded bit stream at a bit rate of 200 Mbps to achieve the real-time performance, while the clock is operated at 74.25 MHz. The result numbers of ALUs are 3266 and the critical path is within 10.5 ns.
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