Minimized reversible synthesis of non-reversible quinary logic function

Reversible multiple-valued logic circuit has several advantages over reversible binary logic circuit. In this paper, we propose a method of minimization of Galois field sum of products (GFSOP) expression for non-reversible quinary logic function. We also propose a method of reversible realization of quinary GFSOP expression as cascade of quinary reversible gates. Experimental results show that a significant minimization can be achieved using the proposed minimization method.